Regviz

Silicon Labs /SiM3_NRND /SIM3L168_A /SPI_1 /CLKRATE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKRATE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3L168_A/SPI_1/CLKRATE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIV

Description

Module Clock Rate Control

Fields

CLKDIV

Clock Divider.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data